Aegis – open-source FPGA silicon
by rosscomputerguy on 4/5/2026, 5:50:04 AM
https://github.com/MidstallSoftware/aegis
Comments
by: smj-edison
As someone who has only dabbled with FPGAs before, this is incredible to see all the steps end-to-end for silicon development! I feel like the articles I've read always leave out details in one part or another, so it's interesting to see all the nix dependencies and build steps.
4/5/2026, 3:04:13 PM
by: mosaibah
The gap this closes is real. IceStorm and Apicula gave you open tooling but you were still loading bitstreams onto someone else's closed fabric. Yosys/nextpnr same story. Aegis is the first time the fabric itself is auditable, which matters a lot for anyone building hardware that needs a complete trust chain from RTL down to GDS. The wafer.space + open PDK path makes it actually tapeout-able, not just a simulation exercise. Curious how the LUT4 fabric competes on density against GF180 commercial offerings, that's usually where open implementations get humbling
4/5/2026, 1:17:20 PM
by: dizhn
There's also an open source Authenticator software with the same name.
4/5/2026, 11:24:31 AM
by: Bluebirt
Neat project - there are already a couple of good open FPGA projects. Have a look at Dirk Koch's and the FABolous teams work. They are doing exceptional work.<p>But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.
4/5/2026, 9:30:20 AM
by: blowback
Excellent. Put me down for a couple.
4/5/2026, 8:56:11 AM